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1. general description the pcu9669 is an advanced single master mode i 2 c-bus controller. it is a fourth generation bus controller designed for data intensive i 2 c-bus data transfers. it has three independent i 2 c-bus channels, one of them with data rates up to 1 mbits/s using the fast-mode plus (fm+) open-drain topology and two with a much larger transmit only transfer rate of up to 5 mbits/s using the new ultra fast-mode (ufm) bus with push-pull topology. each channel has a generous 4352 byte data buffer which makes the pcu9669 the ideal companion to any cpu that needs to transmit and receive large amounts of serial data with minimal interruptions. the pcu9669 is a 8-bit parallel-bus to i 2 c-bus protocol converter. it can be configured to communicate with up to 64 slaves in one se rial sequence with no intervention from the cpu. the controller also has a sequence lo op control feature that allows it to automatically retransmit a stored sequence. its onboard oscillator and pl l allow the controller to g enerate the cl ocks for the i 2 c-bus and for the interval timer used in sequence looping. this feature greatly reduces cpu overhead when data refresh is required in fault tolerant applications. an external trigger input allows data synchronization with external events. the trigger signal controls the rate at which a stor ed sequence is re-transmitted over the i 2 c-bus. error reporting is handled at the transaction level, channel level, and controller level. a simple interrupt tree and interrupt masks allow further customization of interrupt management. the controller parallel bus interface runs at 3.3 v and the i 2 c-bus i/os logic levels are referenced to a dedicated v dd(io) input pin with a range of 3.0 v to 5.5 v. 2. features and benefits ? parallel-bus to i 2 c-bus protocol converter and interface ? 5 mbit/s unidirectional data transfer on ultra fast-mode (ufm) channel (push-pull driver) ? 1 mbit/s and up to 30 ma scl/sda i ol fast-mode plus (fm+) capability ? internal oscillator trimmed to 1 % accuracy reduces ex ternal components ? individual 4352-byte buffers for the fm+ and ufm channels for a total of 13056 bytes of buffer space ? three levels of reset: individual software ch annel reset, global software reset, global hardware reset pin ? communicates with up to 64 slaves in one serial sequence pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller rev. 2 ? 1 july 2011 product data sheet
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 2 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller ? sequence looping wit h interval timer ? supports scl clock stretching (fm+ only) ? jtag port available for boundary scan testing during board manufacturing process ? trigger input synchronizes serial comm unication exactly with external events ? maskable interrupts ? fast-mode plus i 2 c-bus capable and compatible with smbus ? operating supply voltage: 3.0 v to 3.6 v (device and host interface) ? i 2 c-bus i/o supply voltage: 3.0 v to 5.5 v ? latch-up testing is done to jedec standard jesd78 which exceeds 100 ma ? esd protection exceeds 8000 v hbm per jesd22-a114 and 1000 v cdm per jesd22-c101 ? packages offered: lqfp48 3. applications ? add i 2 c-bus port to controllers/processors that do not have one ? add additional i 2 c-bus ports to controllers/processors that need multiple i 2 c-bus ports ? converts 8 bits of parallel data to serial data stream to prevent having to run a large number of traces across the entire printed-circuit board ? entertainment systems ? led matrix control ? data intensive i 2 c-bus transfers 4. ordering information table 1. ordering information type number topside mark package name description version PCU9669B pcu9669 lqfp48 plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 3 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 5. block diagram fig 1. block diagram tck trst tms tdi tdo 002aaf479 usda2 uscl2 v dd(io) 4352-byte buffer oscillator ctrlintmsk ctrlpreset interrupt control buffer control control block ce wr rd int reset power-on/ power-down reset d0 d1 d2 d3 d4 d5 d6 d7 v dd a0 a1 a2 a3 a4 a5 pcu9669 channel 2 ufm i 2 c-bus control status2_[n] control ctrlstatus status1_[n] control channel 1 ufm i 2 c-bus control status0_[n] control transel tranofs slatable tranconfig bytecount intmsk data framecnt refrate scll sclh timeout chstatus preset mode channel 0 fm+ i 2 c-bus control usda1 uscl1 sda0 scl0 4352-byte buffer 4352-byte buffer bus interface trig a6 a7 dc/dc regulator pll transel tranofs slatable tranconfig bytecount intmsk data framecnt refrate sclper sdadly chstatus preset mode transel tranofs slatable tranconfig bytecount intmsk data framecnt refrate sclper sdadly chstatus mode device_id ctrlrdy preset jtag
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 4 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin configuration for lqfp48 PCU9669B d6 d7 a0 v ss a1 a2 a3 v dd v ss v ss a4 scl0 a5 sda0 a6 uscl1 a7 usda1 v dd v ss tck d5 tdi d4 tdo v dd v dd v ss v ss d3 int d2 usda2 v dd uscl2 v ss v ss(io) v dd(io) d1 d0 002aaf480 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24 tms ce trig reset trst v dd rd wr table 2. pin description symbol pin type description a0 3 i address inputs: selects the bus controller?s internal registers and ports for read/write operations. address is registered when ce is low and whether wr or rd transitions low. a0 is the least significant bit. a1 4 i a2 5 i a3 6 i a4 9 i a5 10 i a6 11 i a7 12 i d0 37 i/o data bus: bidirectional 3-state data bus used to transfer commands, data and status between the bus controller and the host. d0 is the least significant bit. data is registered on the rising edge of wr when ce is low. d1 38 i/o d2 41 i/o d3 42 i/o d4 45 i/o d5 46 i/o d6 1 i/o d7 2 i/o
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 5 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller trst 13 i jtag test reset input. for normal operation, hold low (v ss ). tms 14 i jtag test mode select input. for normal operation, hold high (v dd ). tck 15 i jtag test clock input. for normal operation, hold high (v dd ). tdi 16 i jtag test data in input. for normal operation, hold high (v dd ). tdo 17 o jtag test data out output. for normal operation, do not connect (n.c.). int 20 o interrupt request: active low, open-drain, output. this pin requires a pull-up device. usda2 21 o channel 2 ultra fast-mode i 2 c-bus serial data output. push-pull drive. no pull-up device is needed. uscl2 22 o channel 2 ultra fast-mode i 2 c-bus serial clock output. push-pull drive. no pull-up device is needed. usda1 25 o channel 1 ultra fast-mode i 2 c-bus serial data output. push-pull drive. no pull-up device is needed. uscl1 26 o channel 1 ultra fast-mode i 2 c-bus serial clock output. push-pull drive. no pull-up device is needed. sda0 27 i/o channel 0 i 2 c-bus serial data input/output (open-drain). this pin requires a pull-up device. scl0 28 i/o channel 0 i 2 c-bus serial clock input/output (open-drain). this pin requires a pull-up device. wr 31 i write strobe: when low and ce is also low, the content of the data bus is loaded into the addressed register. data are latched on the rising edge of wr . ce may remain low or transition with wr . rd 32 i read strobe: when low and ce is also low, causes the contents of the addressed regist er to be presented on the data bus. the read cycle begins on the falling edge of rd . data lines are driven when rd and ce are low. ce may transition with rd . ce 33 i chip enable: active low input signal. when low, data transfers between the host and the bus controller are enabled on d0 to d7 as controlled by the wr , rd and a0 to a7 inputs. when high, places the d0 to d7 lines in the 3-state condition. during the initialization period, ce must transition with rd until controller is ready. trig 34 i trigger input: provides the trigger to start a new frame. reset 36 i reset: active low input. a low leve l resets the device to the power-on state. internally pulled high through weak pull-up current. v dd(io) 24 power i/o power supply: 3.0 v to 5.5 v. power supply reference for i 2 c-bus pins. sets the voltage reference point for v il /v ih and the output drive rail for the ufm channel. v ss(io) 23 power i/o supply ground. can be tied to v ss . v dd 7, 18, 30, 40, 44, 48 power power supply: 3.0 v to 3.6 v. all v dd pins should be connected together externally. v ss 8, 19, 29, 35, 39, 43, 47 power supply ground. all v ss pins should be connected together externally. table 2. pin description ?continued symbol pin type description
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 6 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 7. functional description 7.1 general the pcu9669 acts as an interface device between standard high-speed parallel buses and the serial i 2 c-bus. on the i 2 c-bus, it acts as a master. data transfer between the i 2 c-bus and the parallel-bus host is carried out on a buffered basis, using either an interrupt or polled handshake. 7.2 internal oscillator and pll the pcu9669 contains an inte rnal 12.0 mhz oscillator and 156 mhz pll which are used for all internal and i 2 c-bus timing. the oscillator and pll require up to t init(po) to start up and lock after power-up. the o scillator is not shut down if the serial bus is disabled. 7.3 buffer description remark: in the following section a ?transaction ? is defined as a contiguous set of commands and/or data sent/received to/from a single slave. a ?sequence? is a set of transactions stored in the buffer. the pcu9669 channels have individual 4352-byte data buffers (see section 7.3.2 ? buffer sizes ? ) that allow several transactions to be executed before an interrupt is generated. this allows the host to request several transactions (up to maximum buffer size on each channel) in a single sequence and lets the p cu9669 perform it without the intervention of the host each time a requested transaction is performed. the host can then perform other tasks while the pcu9669 executes the requested sequences. by following a simple procedure, the i 2 c-bus controller can store several i 2 c-bus transactions directed to different slaves addresses on any of the channels. the transaction stored in the buffer can be of any type, thus reads and writes can be interlaced in a sequence. when multiple slave reads are requested in a sequence, the read data is stored in-line in the sequence and the buffer number must be specified in the transel to provide the read location and the tranofs byte offset value. by default, the tranofs is set to 00h. so let us consider the scenario where the host has done the initialization (mode, masks, and other configuration) and writes data into the buffer of one of the three channels. the host starts by programming the buffer configuration registers tranconfig (number of slaves and bytes per slave) and then the slatable (slave addresses). then the host programs the transel (transaction data bu ffer selection) and the tranofs (byte offset selection) to 00h to set the memory pointers to the beginning of the buffer (the default value is 00h af ter a power-on or reset ). next, the host transfers the data into data until the entire sequence is loaded. if t he transaction is a read transaction, the host must write a dummy byte (i.e., ffh) for each expected serial read byte to reserve the memory space in the buffer for the transaction. care should be taken so as to not overflow the buffer with excessive read/write commands. in the event of an overflow, represented by the be bit in the ctrlstatus register, will be set to logic 1. the int pin will be set low if the bemsk bit in the ctrlintmsk register is logic 0. to recover the channel, a channel reset is required. all configuration and data needs to be checked by the host and resent to the i 2 c-bus controller. (see section 7.3.2 ? buffer sizes ? .)
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 7 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller after sending all the commands and data it wanted to the i 2 c-bus controller, the host could either continue to program data for other channels or write to the control register to begin data transmission on the curr ent channel. th e transactions will be sent on the i 2 c-bus in the order in which the slave addresses are listed in the slatable, separated by a restart condition. the last transaction in the sequence will end with a stop condition. if during a read command a nack on the slave address is received, the buffer space allocated for the read will remain untouched and will co ntain the last information written in that location. a buffer read on the parallel bus should only be done after a valid buffer state is reached to guarantee data valid (see section 7.5.1.1 ? status0_[n], status1_[n], status2_[n] ? transaction status registers ? ). to program data for another channel, that channel is selected and data programmed as described above. one or more channels can be busy with serial transmission while additional parallel-bus data is sent to the buffer of an idle channel. 7.3.1 buffer management assumptions ? repeated starts will be sent betw een two consecutive transactions. ? after the last operation on a channel is completed, a st op will be sent. ? in a read transaction, after the last data byte has been received from a particular slave, a nack is sent to the slave. 7.3.2 buffer sizes the pcu9669 channels have individual buffers assigned to them. the contents of the buffers should only be modified during channel idle states. the memory allocation is 4352 bytes per channel. the buffer sizes represent the memory allocated for the data block only. the slave address table and configuration bytes are contained in other locations and do not need to be included in the required buffer size calculation. for example, to calculate the size of the memory needed to write 26 bytes to 10 slaves and to read 2 bytes from 4 slaves (no command bytes required for the read): 10 slaves ? 26 bytes/slave = 260 bytes for the write transactions 4 slaves ? 2bytes/slave = 8bytes fo r the read transactions a total of 268 bytes of buffer space is required to complete the sequence. remark: note that the bytes required to store the 30 slave addresses are not included in the calculation since they are st ored in the slatable register.
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 8 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 7.4 error reporting and handling in case of any transaction error conditions, the device will load the transaction error status in the statusx_[n], generate an interrupt, if unmasked, by pulling down the int pin and update the chstatus and ctrlstatus registers. the status for the individual sla addresses will be stored in the statusx_[n] registers. in the event of a nack from a slave, there ar e two possible courses of action. the first is that an interrupt will be generated and the cu rrent transaction and sequence terminated. the second is that while the wemsk and/or remsk is a logic 1, a nacked byte will be ignored, and the transmission will continue with the next transac tion in the sequence until the end of the sequen ce. the controller will skip the slav e address and/or data where the nack occurred and move on to the next transaction in the sequence. any error will be reported in the corresponding statusx_[n] regi ster (where ?n? is the buffer number of the slave) or the chstatus or ctrlstatus registers. 7.5 registers the pcu9669 contains several registers that are used to configure the operation of the device, status reporting, and to send and receive data. the device also contains global registers for chip level control and status reporting. the statusx_[n] registers are channel-level direct access registers. the data, slatable, tranconfig, and bytecount registers are auto-increment registers. the memory access pointer to the data registers can be programmed using the transel and tranofs registers. see section 7.5.1.2 ? control ? control register ? , for information on the pointer reset bits bptrrst and aiptrrst.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 9 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller table 3. pcu9669 register address map - direct register access 7 6 5 4 3 2 1 0 register name access write access while ch active description default size (bytes) channel status registers 0 0 channel 0 transaction number (hex) status0_[n] r no individual transaction status (direct address) 00h 64 0 1 channel 1 transaction number (hex) status1_[n] r no individual transaction status (direct address) ([7:2] = 0 in ufm) 00h 64 1 0 channel 2 transaction number (hex) status2_[n] r no individual transaction status (direct address) ([7:2] = 0 in ufm) 00h 64 channel 0 (fm+) registers 11000000control r/w yes [1] channel 0 control 00h 1 0 0 0 1 chstatus r no channel 0 status 00h 1 0 0 1 0 intmsk r/w yes channel 0 interrupt mask 00h 1 0 0 1 1 slatable r/w no channel 0 slave addr ess table (auto-increment) 00h 64 0 1 0 0 tranconfig r/w yes, for trancount [2] channel 0 transaction configuration (auto-increment) 00h 65 0 1 0 1 data r/w yes channel 0 data (auto-increment) 00h bufsize [3] 0 1 1 0 transel r/w yes channel 0 transaction data buffer select 00h 1 0 1 1 1 tranofs r/w yes channel 0 transaction data buffer byte offset 00h 1 1 0 0 0 bytecount r no channel 0 transmitted byte count (auto-increment) 00h 64 1 0 0 1 framecnt r/w no channel 0 frame count 01h 1 1 0 1 0 refrate r/w no channel 0 frame refresh rate 00h 1 1 0 1 1 scll r/w no channel 0 clock low state 5eh 1 1 1 0 0 sclh r/w no channel 0 clock high state 3fh 1 1 1 0 1 mode r/w no channel 0 mode 92h 1 1 1 1 0 timeout r/w no channel 0 time-out 00h 1 1 1 1 1 preset r/w yes channel 0 parallel reset 00h 1
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 10 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller channel 1 (ufm) registers 11010000control r/w yes [1] channel 1 control ([7] = 1) 00h 1 0 0 0 1 chstatus r no channel 1 status ([5:1] = 0 in ufm) 00h 1 0 0 1 0 intmsk r/w yes channel 1 interrupt mask ([5:1] = don?t care) 00h 1 0 0 1 1 slatable r/w no channel 1 slave addr ess table (auto-increment) 00h 64 0 1 0 0 tranconfig r/w yes, for trancount [2] channel 1 transaction configuration (auto-increment) 00h 65 0 1 0 1 data r/w yes channel 1 data (auto-increment) 00h bufsize [3] 0 1 1 0 transel r/w yes channel 1 transaction data buffer select 00h 1 0 1 1 1 tranofs r/w yes channel 1 transaction data buffer byte offset 00h 1 1 0 0 0 bytecount r no channel 1 transmitted byte count (auto-increment) 00h 64 1 0 0 1 framecnt r/w no channel 1 frame count 01h 1 1 0 1 0 refrate r/w no channel 1 frame refresh rate 00h 1 1 0 1 1 sclper r/w no channel 1 clock period 20h 1 1 1 0 0 sdadly r/w no channel 1 sda delay 08h 1 1101mode [4] r/w no channel 1 mode 83h 1 1110- - - reserved 00h 1 1 1 1 1 preset r/w yes channel 1 parallel reset 00h 1 table 3. pcu9669 register address map - direct register access ?continued 7 6 5 4 3 2 1 0 register name access write access while ch active description default size (bytes)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 11 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller channel 2 (ufm) registers 11100000control r/w yes [1] channel 2 control ([7] = 1) 00h 1 0 0 0 1 chstatus r no channel 2 status ([5:1] = 0 in ufm) 00h 1 0 0 1 0 intmsk r/w yes channel 2 interrupt mask ([5:1] = don?t care) 00h 1 0 0 1 1 slatable r/w no channel 2 slave addr ess table (auto-increment) 00h 64 0 1 0 0 tranconfig r/w yes, for trancount [2] channel 2 transaction configuration (auto-increment) 00h 65 0 1 0 1 data r/w yes channel 2 data (auto-increment) 00h bufsize [3] 0 1 1 0 transel r/w yes channel 2 transaction data buffer select 00h 1 0 1 1 1 tranofs r/w yes channel 2 transaction data buffer byte offset 00h 1 1 0 0 0 bytecount r no channel 2 transmitted byte count (auto-increment) 00h 64 1 0 0 1 framecnt r/w no channel 2 frame count 01h 1 1 0 1 0 refrate r/w no channel 2 frame refresh rate 00h 1 1 0 1 1 sclper r/w no channel 2 clock period 20h 1 1 1 0 0 sdadly r/w no channel 2 sda delay 08h 1 1101mode [4] r/w no channel 2 mode 83h 1 1110- - no reserved 00h 1 1 1 1 1 preset r/w yes channel 2 parallel reset 00h 1 table 3. pcu9669 register address map - direct register access ?continued 7 6 5 4 3 2 1 0 register name access write access while ch active description default size (bytes)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 12 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller [1] except tp and te. changing polarity of tp whil e te is active will cause a false trigger. [2] the transaction count (tranconfig[0]) can be wr itten to during the idle period between sequences. [3] refer to section 7.3.2 ? buffer sizes ? for channel memory allocation. [4] unused bits in the ufm register set will return 0b when read and writes will be ignored. [5] controller ready = ffh immediately after por or after a hardware reset or global reset. it will clear (00h) once the initial ization routine is done. global registers 11110000ctrlstatusr yes controller status 00h 1 0 0 0 1 ctrlintmsk r/w yes master interrupt mask 00h 1 0010- r no reserved 08h 0011- r no reserved 00h 0100- r no reserved 00h 0101- r no reserved 00h 0 1 1 0 device_id r no device id e9h 0 1 1 1 ctrlpreset r/w yes master parallel reset 00h 1 1 1 1 1 ctrlrdy [5] r no controller ready register ffh 1 table 3. pcu9669 register address map - direct register access ?continued 7 6 5 4 3 2 1 0 register name access write access while ch active description default size (bytes)
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 13 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 7.5.1 channel registers 7.5.1.1 status0_[n], status1_[n], status2_[n] ? transaction status registers status0_[n], status1_[n], and status2_[n] are 8-bit ? 64 read-only registers that provide status information for a given transaction. only the 5 lower bits are used; the top bits will always read 0. when bits [4:2] are set, a channel interrup t is requested (the int pin is asserted low). a read to statusx_[n] register will clear its status. to clear all the statusx_[n] registers, a by te-by-byte read of all status x_[n] registers is required. the controller will auto-clear the statusx_[n ] registers at each start of a sequence when framecnt = 1 and only at the first start when framecnt ? 1. each register byte can be accessed by direct addressing so that the host can choose to read the status on one or more individual transactions without having to read all 64 status bytes. [1] does not apply to the ufm channel. remark: when statusx_[n] = 00h, no interrupt is requested and the transaction is in the done/idle state. during program execution, the tr and ta bits behave as follows: example, we are to transfer 3 transactions in a sequence. all init ialization is completed (loading of sla, tranconfig, data) and device is ready for serial transfer. before the sta bit is set, the statusx_[n] register will contain: statusx_[0] = 0 statusx_[1] = 0 statusx_[2] = 0 statusx_[3] = 0 : table 4. statusx_[n] - transaction status code register bit description bit symbol description 7:5 st[7:5] always reads 000 4rsn [1] read slave nack. when high, a nack was received after a slave address was transmitted on the serial bus on a read transaction. an interrupt will be requested. 3wsn [1] write slave nack. when high, a nack was received after a slave address was transmitted on the serial bus on a write transaction. an interrupt will be requested. 2wdn [1] write data nack. when high, a nack was received for a data byte during a write transaction on the serial bus. an interrupt will be requested. 1 ta transaction active. when 1, the transaction is currently active on the serial bus. no interrupt is requested. 0 tr transaction ready. when 1, a transaction is loaded in the buffer and waiting to be executed. no interrupt is requested.
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 14 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller after sta is set: statusx_[0] = 2 statusx_[1] = 1 statusx_[2] = 1 statusx_[3] = 0 : since there is no timing requirement in setting the sta bit after the initialization, the device will update the first status when the sta bit is set and will always go fr om 0 to 2 (idle to transaction active). 7.5.1.2 control ? control register control is an 8-bit register. the sto bit is affected by the bus controller hardware: it is cleared when a stop condition is present on the i 2 c-bus. table 5. control - control register bit description address: channel 0 = c0h; channel 1 = d0h; channel 2 = e0h. legend: * reset value bit symbol access value description 7 stoseq r/w stop sequence bit. 1 when the stoseq bit is set while the channel is active, a stop condition will be transmitted immediately following the end of the current sequence being transferred on the i 2 c-bus. no further buffered transactions will be carried out and the channel will return to the idle state. normal error re porting will occur up until the last bit. when a stop condition is detected on the bus, the hardware clears the stoseq flag. 0* when stoseq is reset, no action will be taken. 6 sta r/w the start flag. 1 when the sta bit is set to begin a sequence , the bus controller hardware checks the status of the i 2 c-bus and generates a start condition if the bus is free (does not apply to the ufm channel). if the bus is not idle, then int will go low and the chstatus register will contain a bus error code (either dae or cle will be set). the sta bit may be set only at a valid idle state. the controller will reset the bit under the following conditions: ? a sequence is done and framecnt = 1. ? a sequence loop is done and framecnt > 1. ? the stoseq bit is set, framecnt = 0, and the current sequence is done. ? the stoseq bit is set, framecnt > 1, and the current sequence is done. ? the sto bit is set and the current byte transaction is done. this bit cannot be set if the chen bit is 0. 0* when the sta bit is reset, no start condition will be generated. 5 sto r/w the stop flag. 1 when the sto bit is set while the channel is active, a stop condition will be transmitted immediately following the current data or slave address byte being transferred on the i 2 c-bus. if a read is in progress, a nack will be generated before the stop. no further buffered transactions will be carried out and the channel will return to the idle state. normal error reporting will occur up until the last bit. when a stop condition is detected on the bus, the hardware clears the sto flag. 0* when the sto bit is reset, no action will be taken.
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 15 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller remark: due to a small latency between setting the sta bit and the ability to detect a trigger pulse, if the sta bit is set simultaneously to an incoming trigger pulse, the pulse will be ignored and the contro ller will wait for the next trigger to send the start. if the sto or stoseq bit are set at anytime while the sta bit is 0, then no action will be taken and the write to these bits is ignored. remark: sto has priority over stoseq. 4 tp r/w trigger polarity bit. cannot be changed while channel is active. 1 trigger will be detected on a falling edge. 0* trigger will be detected on a rising edge. 3 te r/w trigger enable (te) bit controls the trigge r input used for frame refresh. te cannot be changed while channel is active. when the tr igger input is enabled, the trigger will override the contents of the framecnt register and will start triggering when sta bit is set. thereafter, when a trigger tick is detected, the controller will issue a start command and the stored sequence will be transferred on the serial bus. 1 when te = 1, the sequence is controlled by the trigger input. 0* when te = 0, the trigger inputs are ignored. 2 bptrrst w 1 resets auto increment pointers for bytecount. reads back as 0. 1 aiptrrst w 1 resets auto increment pointers for slatable and tranconfig. the data register auto-increment pointer will be set to the value that corresponds to transel and tranofs registers. reads back as 0. remark: to reset the data pointer, write 00h to transel. 0 - w 0 reserved. user must write 0 to this bit. table 5. control - control register bit description ?continued address: channel 0 = c0h; channel 1 = d0h; channel 2 = e0h. legend: * reset value bit symbol access value description
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 16 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller table 6. control register bits sta, sto, stoseq operation/behavior channel state (initialization steps) next write action by host results framecnt te sta sto stoseq idle (reset, tranconfig, slatable, data, sta = 0) 1 0 0 x x no action. 1 0 1 x x start transmitted on serial bus followed by sequence stored in buffer. active (reset, load tranconfig, slatable, data, sta = 1 1 0 x 0 x no change; cannot write sta while active. 1 0 x 1 x when the sto bit is set, two actions are possible: 1. if the transaction is a read, a stop is sent after the first read byte (nack sent) and the byte count is updated. 2. if the transaction is a write, a stop is sent after the end of ack cycle of the current byte and bytecnt is updated. the sd bits will be set. refrate loop idle (reset, load tranconfig, slatable, data sta = 1) [1] ? 1 0 0 x x no action. ? 1 0 x 0 1 channel will go immediately to the inactive state and sd and fld bits will be set. [2] ? 1 0 x 1 x channel will go immediately to the inactive state and sd and fld bits will be set. [2] refrate loop active (reset, load, tranconfig, slatable, data, sta = 1) ? 1 0 x 0 0 no action. ? 1 0 x 0 1 stop at end of current frame. the sd and fld bits will be set. ? 1 0 x 1 x when the sto bit is set, two actions are possible: 1. if the transaction is a read, a stop is sent after the first read byte (nack sent) and the byte count is updated. 2. if the transaction is a write, a stop is sent after the end of ack cycle of the current byte and bytecnt is updated. the sd and fld bits will be set. trigger loop idle (reset, load tranconfig, slatable, data, sta = 1) x 1 0 x x no action. x 1 x 0 1 stop at end of current frame. the sd and fld bits will be set. x 1 x 1 x when the sto bit is set, two actions are possible: 1. if the transaction is a read, a stop is sent after the first read byte (nack sent) and the byte count is updated. 2. if the transaction is a write, a stop is sent after the end of ack cycle of the current byte and the bytecnt is updated. the sd and fld bits will be set.
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 17 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller [1] loop idle is defined as the time elapsed from a stop to the start of the next sequence while sta = 1. [2] channel active is defined by the ctrlstatus[5:3] bits. 7.5.1.3 chstatus ? channel status register chstatus is an 8-bit read-only register that provides status information for a given channel. some of these status bits are erro r codes that cannot be masked (nmi) by the intmsk register and need attention from the host. all these status drive the int pin active low. to clear the individual chan nel interrupt request, you must read the chstatus register. the be interrupt is clea red by reading the ctrlstatus register. after the chstatus register is cleared, only new errors or status updates will cause the chstatus bits to be set. [1] does not apply to ufm channel. always read as logic 0. the dae, cle and sse bits corres pond to bus error states, and the fe bit corresponds to host programming errors. dae - sda error bit: this bit indicates that the sd a line is stuck low when the pcu9669 is trying to send a start condition. cle - scl error bit: this bit indicates that the scl line is stuck low. trigger loop active (reset, load tranconfig, slatable, data, sta = 1) x 1 x 0 0 no action. x 1 x 0 1 channel will go immediately to the inactive state and sd and fld bits will be set. [2] x 1 x 1 x channel will go immediately to the inactive state and sd and fld bits will be set. [2] table 6. control register bits sta, sto, stoseq operation/behavior ?continued channel state (initialization steps) next write action by host results framecnt te sta sto stoseq table 7. chstatus - channel and buffer status codes register bit description address: channel 0 = c1h; channel 1 = d1h; channel 2 = e1h. bit symbol description 7 sd sequence done. the sequence loaded in the buffer was sent and stop issued on the serial bus. 6 fld frame loop done. the framecnt val ue has been reached. a stop has been issued on the bus. 5we [1] write error detected in transaction. an sla nack or data nack was detected in a write transaction of the sequence. 4re [1] read error detected in transaction. an sla nack was detected in a read transaction of the sequence. 3dae [1] bus error, sda stuck low. 2cle [1] bus error, scl stuck low. 1 sse [1] bus error, illegal start or stop detected. 0 fe frame error detected. the time required to send the sequence exceeds refresh rate programmed to the refrate regist er or the time be tween trigger ticks.
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 18 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller sse - illegal start/st op detected bit: this bit indicates that a bus error has occurred during a serial transfer. a bus error is caused when a start or stop condition occurs at an illegal position in the format frame. exampl es of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. a bus error may also be caused when external interferenc e disturbs the internal pcu9669 signals. fe - frame error bit: this bit indicates that the time required to send the sequence exceeds the refresh rate programmed in the refrate register or the time between trigger ticks. solving frame erro rs include programming longer refresh rates, speeding up the bus frequency, shortening the amount of bytes sent/received in the sequence, or increasing the time between trigger ticks. if the frame error is mask ed by the femsk, the device will continue to tran smit transactions until the end of the se quence without re-starting the sequence even if new triggers are detected. the total number of sequences transmitted will be the number stored in the framecnt register. once a complete sequence is transmitted, a new sequence will initiate when a subsequent trig ger appears. the fe flag will be held high and sequen ces will still be transmitted unless chstatus is read. if the frame error is unmasked, the sequence will be aborted at the next logical stopping point (i.e., for a read transaction a nack will be sent), a stop transmitted and an interrupt will be generated. since the controller terminates the sequence in a controlled mechanism, there may be a 2-byte delay if a frame error (fe) is detected during a read transaction. the fe bit is set after the stop is detected on the bus. a. sequence fully executed within the pe riod programmed in refrate register this condition causes a frame error and the fe bit to be set. b. sequence exceeds period programmed in refrate register, femsk = 0 c. sequence exceeds period programmed in refrate register, femsk = 1 fig 3. frame error detection 002aaf247 sequence a sequence a sequence a 10 ms 10 ms 10 ms time 002aaf627 sequence b 10 ms 10 ms 10 ms time frame error detected, data not sent after fe 002aaf628 sequence c 10 ms 10 ms 10 ms time frame error detected, femsk = 1, data sent after fe sequence c
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 19 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 7.5.1.4 intmsk ? interrupt mask register through the intmsk register, there is the op tion to manage which states generate an interrupt, allowing more control from the host on the transaction. the interrupt mask applies to all tran sactions in a given channel. a bit se t to 1 indicates th at the mask is active. the intmsk register default is all interrupts are un-masked (00h). table 8. error detection operation/behavior channel state ar (mode register) error detected (chstatus) next action dae cle sse active or idle x 0 0 1 interrupt set, if a transaction is active it will be immediately aborted and no further action taken by controller. host to re-initialize bus (i.e., force a bus recovery), reset slaves, or take other appropriate recovery action. after bus is recovered, host to re-start transaction. active or idle, time-out enabled, and clock line is low x 0 1 0 interrupt set, active transaction will be immediately aborted and no further action taken by controller. no bus recovery possible by bus-controller. host to recover bus by resetting slaves or system. after bus is recovered, host to re-start transaction. active and at a start or repeated-start condition 1 0 0 0 interrupt not set, active transaction will be immediately aborted and a bus recovery will be attempted by the bus-controller. if successful, a start will be issued automatically and the serial transfer will continue normally at the location of the failed transaction. no host action is required. 1 1 0 0 interrupt set, an auto-recovery was attempted and failed. active transaction will be immediately aborted and the bus-controller determines bus recovery actions, for example setting the br bit or resetting the slaves. 0 1 0 0 interrupt set, active transaction will be immediately aborted and no bus recovery will be attempted by the bus-controller. host may attempt a bus recovery by setting the br bit or determine other bus recovery action. table 9. intmsk - interrupt mask register bit description address: channel 0 = c2h; channel 1 = d2h; channel 2 = e2h. bit symbol description 7 sdmsk sequence done mask. the end of se quence interrupt will not be generated. 6 fldmsk frame loop done mask. a frame loop done interrupt will not be generated. the controller will enter the idle state. 5 wemsk [1] write error mask. an sla nack or data nack interrupt will not be generated and the controller will skip the remaining write data in the transaction and continue with the start of the next transaction in the sequence. 4 remsk [1] read error detected in transaction. an sla nack interrupt will not be generated and the controller will skip the read transaction and continue with the start of the next transaction in the sequence.
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 20 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller [1] does not apply to ufm channel. 7.5.1.5 slatable ? slave address table register slatable is an 8-bit ? 64 register set that makes up a t able that stores the slave address for each transaction in the sequence. the table is loaded by using an auto-increment pointer that is not user-accessible. to reset the pointer, the aiptrrst bit must be set in the control register. the slave addresses in the slatable register are stored with a zero-based (n ? 1) index. the first slave addre ss occupies the 00h position. remark: slave address entries greater than the transaction count are not part of the sequence. tranconfig[0] cont ains the transaction count that will be included in the sequence. 3:1 - reserved 0 femsk frame error mask. a frame error interrupt will not be generated. remark: use caution and good judgem ent when using this mask. unexpected/erratic behavior may result in the slave devices. table 9. intmsk - interrupt mask register bit description ?continued address: channel 0 = c2h; channel 1 = d2h; channel 2 = e2h. bit symbol description table 10. slatable - slave address table register bit description address: channel 0 = c3h; channel 1 = d3h; channel 2 = e3h. bit symbol description 7:1 slatable[7:1] slave address. 0 slatable[0] when 1, a read transaction is requested. when 0, a write transaction is requested. table 11. example of slatable registers transaction slave address 00h 10h 01h 12h 02h 28h 03h 40h 04h 14h :: 3fh 36h
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 21 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 7.5.1.6 tranconfig ? transacti on configuration register the tranconfig register is an 8-bit ? 65 register set that makes up a table that contains the number of transa ctions that will be executed in a sequence and the number of data bytes involved in the transaction. the first byte of the register is the transact ion count register. the remaining 64 registers are the transaction length registers. remark: even if the transaction length (tranconfig[1:40h]) and the slatable([0:3fh]) are fully init ialized, only the specified number of transactions in the transaction count (tranconfig[0]) will be part of the sequence. if the transaction count is 0, th en there will be no activity on th e serial bus if the sta bit is set. in addition, there will be no interrupts generated or st atus updated. th e controller will simply reset the control.sta bit wit hout performing any transactions. if the transaction length is 0, a read transaction will be sk ipped and a write transaction will send the slave address plus write bit (sla +w) on the serial bus with no data bytes. 7.5.1.7 data ? i 2 c-bus data register data is an 8-bit read/write, auto-increment regi ster. it is the interface port to the channel buffer. when accessing the buffer, the host writes a byte of serial data to be transmitted or reads bytes that have just been received at this location. the host can read from the data at any time and can only write to this 8-bit register while the channel is idle. remark: reading the data when the serial interf ace is active may return outdated or erroneous data. the host can read or write data up to the amount of memory space allotted to the channel. the location at which the data is accessed is stored in the transel and tranofs register (both default at 00h). table 12. tranconfig, byte 0 - transaction co nfiguration register bit description address: channel 0 = c4h; channel 1 = d4h; channel 2 = e4h. bit symbol description 7:0 number of transactions in the sequence. maximum is 40h. table 13. tranconfig, byte 1 to 40h - transactio n configuration regi ster bit description bit symbol description 7:0 number of bytes per transaction in the sequence. maximum is ffh. table 14. example of tranconfig register loaded register value description transaction count 10h 16 transactions = 16 slave addresses in the slatable transaction length 00h 0ah 10 byte transaction transaction length 01h 12h 18 byte transaction transaction length 02h 28h 40 byte transaction transaction length 03h 40h 64 byte transaction ::: transaction length 3fh 12h 18 byte transaction
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 22 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller to return to the data location pointed by the contents of the transel and tranofs register after read or write access to the data register, set the aiptrrst (auto-increment pointer reset) bit in the control register. to return to the first data register loca tion in the buffer set the transel to 00h. 7.5.1.8 transel ? transaction data buffer sel ect register the transel register is used to select the po inter to a specific transaction in the data buffer. this allows the user to update the data of a specific slave without having to re-write the entire data buffer or to read back the stored serial data from a read transaction. the value of this register is the slave addre ss position in the slatable register. the transel register is zero-based (n ? 1) register. for example, if a change to the 22nd slave address data is required, the host would set the transel register to 15h. this register can be used in conjunction with the transofs register to access a specific by te in the data buffer. the host would then proceed to write the new data to the data r egister. the auto-increm ent feature continues to operate from this new position in the data register. setting transel to an uninitialized tr anconfig entry may cause a request to read/write data outside the data buffer. if this occurs, the be bit in the ctrlstatus register will be set to a logic 1. write data w ill be ignored and read data will be invalid. when a new transaction is selected by programming the transel registers, the transofs register will automat ically be reset to 00h. remark: when updating the data buffer, if the number of bytes to be updated or read exceeds the number of bytes that were specified in the tranco nfig register, the auto-increment will go over the transaction boundary into the next tran saction stored in the buffer. remark: to reset the data pointer, write 00h to the transel register. table 15. data - data register bit description address: channel 0 = c5h; channel 1 = d5h; channel 2 = e5h. bit symbol description 7:0 d[7:0] eight bits to be transmitted or just received. a logic 1 in data corresponds to a high level on the i 2 c-bus. a logic 0 corresponds to a low level on the bus. table 16. transel - transaction data buffer select register bit description address: channel 0 = c6h; channel 1 = d6h; channel 2 = e6h. bit symbol description 7 - reserved. 6 - reserved. 5:0 transel[5:0] slave address position in the slatable. the maximum number is 3fh.
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 23 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 7.5.1.9 tranofs ? transaction data buffer byte select register in conjunction with the transel register, the tranofs register is used to select the pointer to a specific byte in a transaction in the data buffer. this allows the user to read or re-write a specific data byte of a specific slave without having to read/re-write the entire data buffer. the tranofs register is zero-based (n ? 1), so the maximum bytes this register will point to is 256. for example, if the tenth byte in the 40th sl ave address data is required, the host would set the transel register to 27h and the tr ansofs register to 09h. the host would then proceed with a read to the data register. setting tranofs to a byte offset outside of the data buffer will cause the be bit in the ctrlstatus register will be set to a logic 1. write data will be ignored and read data will be invalid. remark: the number of bytes to be updated or read should not exceed the number of bytes that were specified in the tran config register. doing so will cause the auto-increment to go over the transaction boundary into the next transaction stored in the buffer. 7.5.1.10 bytecount ? transmitted an d received byte count register the bytecount register stores the number of bytes that have been sent or received. the count is continuously upda ted, therefore the bytecount is a real time reporting of transmitted and received bytes. this is a read-only register. the bytecount includes only the bytes that have been acked in a wr ite transaction and all bytes received in a read transaction including in transactions where the wemsk or remsk are enabled and part or complete transactions have been skipped (see figure 9 ). the bytecount register is cleared at the start of every sequence. 7.5.1.11 framecnt ? frame count register this register is a read/write register. the contents of this register holds the programmed value by the host and is not a real-time c ount of frames sent on the serial bus. if the framecnt is 00h, the sequence stored in the buffer will loop continuously. a stop will be sent at the end of each sequence. table 17. tranofs - transaction data buffe r byte select register bit description address: channel 0 = c7h; channel 1 = d7h; channel 2 = e7h. bit symbol description 7:0 tranofs[7:0] byte index for the specified transaction buffer in transel. table 18. bytecount, byte 0 - transaction configuration register bit description address: channel 0 = c8h; channel 1 = d8h; channel 2 = e8h. bit symbol description 7:0 bytecount[7:0] number of bytes sent/rec eived per transaction in the sequence. maximum is ffh. table 19. framecnt - frame count register bit description address: channel 0 = c9h; channel 1 = d9h; channel 2 = e9h. bit symbol description 7:0 framecnt[7:0] bit 7 to bit 0 indicate the number of times buffered commands are to be re-transmitted. default is 01h.
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 24 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller if the framecnt is 01h, it is defined as the default state and the sequence stored in the buffer will be sent once and a stop will be sent at the en d of the sequence. if the framecnt is greater than 01h, the sequence stored in the buffer will loop framecnt times and a stop will be sent at the end of each sequence. remark: the framecnt can only be set to loop on the sequence stored in the buffer. 7.5.1.12 refrate ? refresh rate register the refrate register defines the time period between each sequence start when refrate looping is enabled (framecnt ? 1, and te = 0). the refresh period defined by refrate should always be programmed to be greater than the time it takes for the se quence to be transferred on the i 2 c-bus. if the refrate values is too small, the fram e error (fe) bit will be set an d an interrupt will be requested. remark: if the framecnt is 1, then the re fresh rate function will be disabled. 7.5.1.13 scll, sclh and sclper, sdadly ? clock rate registers the clock rate register for the standard-mode , fast-mode, and fast -mode plus (fm+) is controlled by the scll and sclh registers and the for the ultra fast-mode channel by the sclper and sdadly registers. they define the data rate for the serial bus of the pcu9669. the actual frequency on the serial bus is determined by t high (time where scl is high), t low (time where scl is low), t r (rise time), and t f (fall time) values. writing illegal values into the scll and sclh registers or sclper registers will cause the part to operate at the respective maximum channel frequency. for standard, fast, and fast-mode plus, t high and t low are calculated based on the values that are programmed into sclh and scll registers and the pll clock frequency. for ufm mode, the clock is a fixed 50 % duty cycle defined by the sclper. in both cases t r and t f are system/application dependent. table 20. refrate - refresh rate register bit description address: channel 0 = cah; channel 1 = dah; channel 2 = eah. bit symbol description 7:0 refrate[7:0] bit 7 to bit 0 indicate the sequence refresh period. the resolution is 100 ? s. the default value is 00h, the ti mer is disabled, and the sequences will be sent back-to-back if the framecnt is = 0 or framecnt is > 1. table 21. scll - clock rate low register bit description (standard-mode, fast-mode, fast-mode plus) address: channel 0 = cbh. bit symbol description 7:0 l[7:0] eight bits defining the lo w state of scl. default: 94 (5eh). table 22. sclh - clock rate high register bit description (stand ard-mode, fast-mode, fast-mode plus) address: channel 0 = cch. bit symbol description 7:0 h[7:0] eight bits defining the high state of scl. default: 63 (3fh).
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 25 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller remark: the mode register needs to be pr ogrammed before programming the scll and sclh registers in order to know which i 2 c-bus mode is selected. see section 7.5.1.14 ? mode ? i 2 c-bus mode register ? for more detail. fast-mode plus (fm+) is the default sele cted mode at power-up or after reset. the clock is derived from the internal pll frequency which is set at 156 mhz (13 ?? osc clock). given a 1 % accuracy on the internal clock, the worst case t pll is . calculating clock settings for standard, fast, and fast-mode plus: (1) the scale factor is set by the mode register and used in the total_scllh calculation. the scale factor is 8 for standard-mode, 4 for fast-mode, and 1 for fast-mode plus. the scll and sclh can be found by: (2) (3) remark: the contributions for the rise time (t r ) and fall time (t f ) are adjusted internally by hardware to match the desired frequency. if an invalid number is written to scll or sclh such that it violates the spec ification, then the controller w ill adjust the bus frequency to the allowable scll and sclh minimums. sample resulting scl frequencies: table 23. scl calcul ation scale factor i 2 c-bus mode frequency scale factor standard 100 khz 8 fast 400 khz 4 fast-mode plus 1000 khz 1 table 24. typical scl frequencies data shown under following conditions: pull-up resistor r pu =500 ? ; bus capacitance c b =~170pf. desired frequency (khz) actual frequency (khz) scll sclh standard-mode (sm) 100 99.3 116 79 90 90.0 129 87 80 80.0 145 98 70 69.5 168 112 60 59.7 194 132 50 50.0 233 156 1 12.12 mhz 13 ? --------------------------------------- - 1 157.56 mhz ------------------------------ - 6.347 ns == total _ scllh 1 t pll freq ? ---------------------------- - scale factor ? = scll 0.6 total ? _ scllh = sclh 0.4 total ? _ scllh =
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 26 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller remark: the correct mode setting should be programmed based on desired frequency since the bus controller will internally select the appropriate t r and t f for the selected mode. the minimum i 2 c-bus frequency is 50 khz. remark: the actual scl frequency will be affect ed by the pll frequency and the bus load. the controller will adjust the scl timing by monitoring the rise time on the scl line and bring the output frequency as close to the programmed value as possible without violating the i 2 c-bus specification for minimum clock high and low timing. fast-mode (fm) 400 398.4 58 39 350 348.7 66 45 300 298.2 78 52 250 250.2 93 62 200 198.0 117 79 150 150.1 155 104 100 100.0 233 156 fast-mode plus (fm+) 1000 999.0 90 63 900 900.0 100 70 800 798.3 113 79 700 698.5 130 90 600 599.9 152 105 500 499.5 183 126 400 399.7 229 158 table 24. typical scl frequencies ?continued data shown under following conditions: pull-up resistor r pu =500 ? ; bus capacitance c b =~170pf. desired frequency (khz) actual frequency (khz) scll sclh
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 27 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller calculating clock settings for ultra fast mode (ufm): the clock period is defined as follows (50 % duty cycle): (4) the data will be delayed with respect to the falling edge of the clock as follows: (5) [1] the minimum allowable value that can be stored in sclper is 32. [2] the minimum allowable value that can be stored in sdadly is 2. the pcu9669 will force a 50 % duty cycle by shifting the cont ents of the sclper register right by 1. when the user writes the sclper register , the sdadly will be loa ded automatically with a value 1 4 the value of sclper (sclper register value right shifted twice). the user can then overwrite the sdadly register if desired. the order in which the registers should be wr itten is first the scl per, then the sdadly register to adjust the delay. the maximum value for sdadly is the preferred value to be loaded. table 25. sclper - clock period register bit description (ultra fast mode) address: channel 1 = dbh; channel 2 = ebh. bit symbol description 7:0 l[7:0] eight bits defining the clock period (ultra fast mode). default 32 (20h). table 26. sdadly - sda delay register bit description (ultra fast mode) address: channel 1 = dch; channel 2 = ech. bit symbol description 7:6 h[7:6] reserved. read only read back zero. 5:0 h[5:0] six bits defining the sda delay (ultra fast mode). default: 8 (08h). table 27. sample clock period and allowable data delay frequency sclper [1] sdadly [2] 5.0 mhz 32 2 to 8 4.0 mhz 39 2 to 9 3.0 mhz 53 2 to 13 2.0 mhz 79 2 to 19 1.0 mhz 158 2 to 39 sclper min ?? 1 t pll freq ? ---------------------------- - = sdadly max ?? sclper 4 ---------------------- - =
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 28 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 7.5.1.14 mode ? i 2 c-bus mode register mode is a read/write register. it contains t he control bits that select the bus recovery options, and the correct timing parameters. timing paramete rs involved with ac[1:0] are t buf , t hd;sta , t su;sta , t su;sto , t high , t low . the auto recovery and bus recovery bits are contained in this register. they control the bus recovery sequence as defined in section 8.5.1 ? i 2 c-bus obstructed by a low level on sda (dae) ? . remark: chen bit value must be changed only when the i 2 c-bus is idle. remark: any change in the ac[1:0] bits (fast-mode to standard-mode, for example) may cause the high and low timings of scl to be violated. it is then required to program the scll and sclh registers with values in accordance with the selected mode. table 28. mode - i 2 c-bus mode register bit description address: channel 0 = cdh; channel 1 = ddh; channel 2 = edh. bit symbol description 7 chen channel enable bit. r/w. 0: channel is disabled, scl and sda high -impedance, usda and uscl driven high. all registers are accessible for setup and configuration, however a sequence cannot be started if the chen bit is 0 (sta cannot be set). 1 (default): channel is enabled. 6- reserved. 5 br bus recovery. when br is set to 1, the bus controller will attempt a bus recovery by sending 9 clock pulses on the bus. once the bus recovery is complete, the controller will reset the bit to 0. this bi t is not intended to generate random or asynchronous 9 clock pulses on the bus. this function is performed automatically when the ar bit is 1. 4 ar auto recovery. when ar = 1 (default), the bus controller will automatically atte mpt to recover the bus as described in section 8.5.1 ? i 2 c-bus obstructed by a low level on sda (dae) ? . when ar = 0, the bus controller will abort the current transaction and generate an error code by setting the dae bit in t he chstatus register and pulling the int pin low. 3:2 - reserved. fm+ channel 0 1:0 ac[1:0] i 2 c-bus mode selection to ensure proper timing parameters (see table 29 and ta b l e 4 0 ). ac[1:0] = 00: standard-mode ac parameters selected. ac[1:0] = 01: fast-mode ac parameters selected. ac[1:0] = 10 (default): fast-mode plus ac parameters selected. ac[1:0] = 11: reserved. ufm channel 1 and channel 2 1:0 ac[1:0] i 2 c-bus mode selection to ensure proper timing parameters (see table 29 and ta b l e 4 0 ). ac[1:0] = 00: reserved. ac[1:0] = 01: reserved. ac[1:0] = 10: reserved. ac[1:0] = 11 (default): ult ra fast-mode ac parameters selected. read-only bits.
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 29 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller remark: the ac[1:0], br and ar bits are not applicable to the ufm channel, they are read-only bits. the ufm channel ac parameters are controlled internally. [1] using the formula 7.5.1.15 timeout ? time-out register timeout is an 8-bit read/write register. it is used to determine th e maximum time that scl is allowed to be in a low logic state before a cle interrupt is generated. remark: the timeout does not apply to the ufm channel of the controller. when the i 2 c-bus interface is operating, timeout is loaded in the time-out counter at every low scl transition. the time-out register can be used in the following cases: ? when the bus controller wants to send a start condition and the scl line is held low by some other device. then the bus c ontroller waits a time period equivalent to the time-out value for the scl to be releas ed. in case it is not released, the bus controller concludes that there is a bus error, sets the cle bit in the chstatus register, generates an interrupt signal and releases the scl and sda lines. ? the time-out feature starts every time th e scl goes low. if scl stays low for a time period equal to or greater than the ti me-out value, the bus controller concludes there is a bus error and behaves in the manner described above. when the i 2 c-bus interface is operating, timeout is loaded in the time-out counter at every scl transition. see section 8.7 ? global reset ? for more information. table 29. i 2 c-bus mode selection example i 2 c-bus frequency (khz) [1] scale factor ac[1:0] mode 100 8 00 standard 400 4 01 fast 1000 1 10 fast-mode plus - - 11 reserved f scl 1 t pll scll sclh + ?? sf ? ?? t r t f ++ ---------------------------------------------------------------------------------------- - = table 30. timeout - time-out register bit description address: channel 0 = ceh. bit symbol description 7 te time-out enable/disable te = 1: time-out function enabled te = 0: time-out function disabled 6:0 to[6:0] time-out value. the ti me-out period = (timeout[6:0] + 1) ? 200 ? s. the time-out value may vary some, and is an approximate value.
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 30 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 7.5.1.16 preset ? i 2 c-bus channel parallel software reset register preset is an 8-bit write-only register. programming the preset register allows the user to reset each individual pcu9669 channel under software control. the software reset is achieved by writing two consecutive bytes to this register. the first byte must be a5h while the second byte must be 5ah. the writes mu st be consecutive and the values must match a5h and 5ah. if this sequence is not follo wed as described, the reset is aborted. the preset resets state-machines , registers, and buffer poin ters to the default values, zeroes the tranconfig, slatable, bytecount, and data arrays of the respective channel and will not reset the enti re chip. the parallel bus rema ins active while a software reset is active. the user ca n read the preset register to determine when the reset has completed, preset returns all 1s when the re set is active and all 0s when complete. 7.5.2 global registers 7.5.2.1 ctrlstatus ? controller status register the ctrlstatus register reports the status of the controller, including the interrupts generated by the parallel bus. there are si x status bits. when ctrlstatus contains 00h, it indicates the idle state and therefore no serial interrupts are requested. the content of this register is continuously updated during the operation of the controller. the lower 3 bits represent the channels that have an interrupt request pending. to clear the individual channel interrupt request, you must read the chstatus register. bits [5:3] indicate if a channel is currently acti ve or if it is in the idle state. remark: a global reset will reset all ch annels and configuration settings. be - buffer error bit: this bit indicates that a buffer error has been detected. for example, a buffer overflow due to the host pr ogramming too many byte s will set this bit. a software or hardware reset is necessary to recover from a buffer error. table 31. preset - i 2 c-bus channel parallel software reset register bit description address: channel 0 = cfh; channel 1 = dfh; channel 2 = efh. bit symbol description 7:0 preset[7:0] read/write r egister used during an i 2 c-bus channel parallel reset command. table 32. ctrlstatus - interrupt status register bit description address: f0h. bit symbol description 7 be buffer error. a buffer error such as overflow has been detected. 6- 5 ch2act channel 2 is active. 4 ch1act channel 1 is active. 3 ch0act channel 0 is active. 2 ch2intp channel 2 interrupt pending. 1 ch1intp channel 1 interrupt pending. 0 ch0intp channel 0 interrupt pending.
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 31 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller the buffer error may occur when a data locati on is being read or written to that has not previously been configured by the tranconfig register. the buffer error can occur on a parallel data write or read beyond the buffer capacity, or setting the transel and tranofs pointers beyond the buffer boundary. when the data register is loaded with data th at goes beyond the capacity of the buffer, the bytes that go over the buffer size will be ignored and a buffer error (be) will be generated. special case: the be interrupt is cleared by readi ng the ctrlstatus register. all other interrupts are cleared by reading the respective chstatus register. see ta b l e 7 for channel status. 7.5.2.2 ctrlintmsk ? control interrupt mask register the ctrlintmsk masks all interrupts generated by the masked channel. this allows the host mcu to complete other operations before servicing the interrupt without being interrupted by the same channel. fig 4. pcu9669 status reporting logic 002aag093 dae cle sse sd we re fe fld ch0intp (fm+) sd fe fld ch1intp (ufm) sd fe fld ch2intp (ufm) table 33. ctrlintmsk - control interrupt mask register bit description address: f1h. bit symbol description 7 bemsk buffer error mask. a buffer error interrupt will not be generated. remark: use caution and good judgement when using this mask. unexpected/erratic behavior may result in the slave devices. 6:3 - reserved 2 ch2msk when this bit is set to 1, all interrupts for the channel will be masked and the int pin will not be pulled low. 1 ch1msk when this bit is set to 1, all interrupts for the channel will be masked and the int pin will not be pulled low. 0 ch0msk when this bit is set to 1, all interrupts for the channel will be masked and the int pin will not be pulled low.
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 32 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller see ta b l e 9 for interrupt mask. 7.5.2.3 device_id ? device id the device_id register stores the bus controller part number so it can be identified on the parallel bus. fig 5. pcu9669 interrupt logic sd sdmsk we wemsk re remsk fe femsk fld fldmsk dae cle sse ch0msk ch0 interrupt sources and masks ch1msk ch1 interrupt sources and masks ch2msk ch2 interrupt sources and masks to int pin bemsk be sd sdmsk fe femsk fld fldmsk sd sdmsk re remsk fe femsk fld fldmsk 002aag094 table 34. device_id - device id register bit description address: f6h. bit symbol description 7 u/a selects pcu or pca device. 1 = pcu96xx 0 = pca96xx 6:0 bcd bcd (binary coded decimal) code of the ending 2 digits for id. range is 00h to 79h. the code for the pcu9669 is e9h.
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 33 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 7.5.2.4 ctrlpreset ? parallel software reset register ctrlpreset is an 8-bit write-only regist er. programming the ctrlpreset register allows the user to reset the pcu9669 under software control. the software reset is achieved by writing two consecutive bytes to this register. the first byte must be a5h while the second byte must be 5ah. the writes mu st be consecutive and the values must match a5h and 5ah. if this sequence is not follo wed as described, the reset is aborted. 7.5.2.5 ctrlrdy ? controller ready register ctrlrdy (address ffh) is an 8- bit read-only register. it indicates the internal state of the controller. when the register is ffh, the co ntroller is in the init ialization state. the initialization state will be entere d at power-up, after a hardware reset, or after a global software reset. the oscillator and the pll will be initialized only after a power-on reset (por), a hardware reset, or a global software reset (ctrlpreset). when the register is 00h, the controller is in the normal operating mode. access while the controller is initializing requires ce pin follow the rd pin transitions to update the state of the controller that is read back. after controller is ready, the ce pin can be held low while rd and wr pins transition. see figure 6 , figure 7 and figure 8 . table 35. ctrlpreset - para llel software reset re gister bit description address: f7h. bit symbol description 7:0 ctrlpreset[7:0] write-only register used during a device parallel reset command. table 36. ctrlrdy - controller ready register bit description address: ffh. bit symbol description 7:0 ctrlrdy[7:0] read-only register indicates the internal state of the controller. ffh indicates the controller is initializing, 00h indicates controller is in normal operating mode. fig 6. during initialization, ce must transition with rd at each read operation 002aag095 ce 00h ffh ffh initializing ready rd data
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 34 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 8. pcu9669 operation the pcu9669 is designed to efficiently transmit and receive large amounts of data on a single master bus. there are three major components that compose the architecture of the i 2 c-bus controller that interact with each othe r to provide a high throughput and a high level of automation when it conducts transactions: ? slave address table: specifies the address of the slaves on the bus and the direction (read or write). ? transaction configuration: specifies the size of the transaction. ? data buffer: contains the data to be transmitted or received from the slave. these three components are integrated in the pcu9669 to build a sequence. a sequence is a set of read or write transactions and th e minimum sequence size is one read or write transaction. several transactions can be st ored in one sequence and be executed without the intervention of the host controller (cpu ) through loop control and using the built-in refresh rate timers. the pcu9669 executes tr ansactions in the order they were loaded into the buffer without interrupting the host. once the end of a sequen ce is reached, the sequence done (sd) bit will be asserted in the chstatus register and the controller will reques t an interrupt, if sdmsk = 0. at this point, the host can rel oad the buffer with a new sequence or resend the one that is currently loaded in the buffer. when a sequence is in progress, no interrupts are generated unless there is an error when a transaction is con ducted. the host will only rece ive an interr upt when the sequence is done. the pcu9669 will dynam ically shift between being a master fig 7. during normal operation, ce may remain low while rd transitions during multiple reads fig 8. during normal operation, ce may remain low while wr transitions during multiple writes 002aag096 ce address z address y address x rd data read address z read address y read address x addr 002aag097 ce data z data y data x wr data write address z write address y write address x addr
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 35 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller transmitter or a master receiver according to the direction bits specified in the slatable. the host ha s the ability to retrieve stored se rial data as soon as a read transaction is done, while the controller ca rries on the remaining transactions in the sequence. 8.1 sequence execution sequences can have transactions of two types: ? write transactions, where the pcu966 9 will behave as a master transmitter ? read transactions, where the pcu9669 will behave as a master receiver on the fm+ channel only, since ufm channels are uni-directional data transfers in each direction are shown in figure 9 . this figure contains the following abbreviations: s ? start condition sla ? 7-bit slave address r ? read bit (high level at sda) w ? write bit (low level at sda) a ? acknowledge bit (low level at sda) a ? not acknowledge bit (high level at sda) data ? 8-bit data byte p ? stop condition in figure 9 , circles are used to indicate when a bit is set in the chstatus register. a channel interrupt is not requested when chstatus = 00h and the int pin is not asserted when the interrupt is masked (see section 7.5.2.2 ). for a successful sequence execution, all th ree components mentioned above must exist in the memory and must be correctly set up. there are not safeguards against programming incorrect transaction sizes, data buffer lengths, or direction bits. if the transaction length is set to 00h, then only the slave addr ess with direction bit will be transmitted. once the host has configured the serial port and programmed the tranconfig (number of slaves and bytes per slave), the slatabl e (slave addresses), transel (transaction data buffer selection) and the tranofs (byte offset selection) and loaded the serial data into the data buffer, the sequen ce is ready to be transmitted. to send the sequence, the host will set the sta bit in the control register and the controller will immediately send a start on the serial bus. then, the transactions will be carried out in the order they appear in the slatable, each being separated by a restart command. if the interrupts are unmasked, the serial transfer will be conducted with out generating interrupts in between transactions. once all tr ansactions are successfully completed, the controller will generate a stop, the sequence done bit (sd) will be set in the chstatus and an interrup t will be generated.
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 36 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller when the interrupts ar e unmasked, a nack on slave address or data (in a write cycle) will terminate the serial transfer, generate a stop, and the int pin will be asserted. the host can read the ctrlstatus (controller status register) to determine which channel generated the interrupt, then it can read the chstatus register of the channel and the statusx_[n] to determine which slave address caused the error. if the interrupts wemsk and remsk are set, then a nack on slave address or data (in a write cycle) will not terminate the serial transfer, the error will be stored in the statusx_[n] register and the serial transfer will continue with the ne xt transaction in the sequence. once all tr ansactions are comple ted, the controller will generate a stop and the sequence done bit (sd) and other error bi ts (we or re) will be set in the chstatus and an interrup t will be generated. if the host wants to poll the p cu9669, it can mask all registers including the sd bit and read the ctrlstatus, chstatus, statusx_[n], and/or the control registers to determine the state of the controller.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 37 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller example chstatus codes: 80h: sequence done with no errors c0h: frame loop and sequence done with no errors a0h: sequence done with a write error d0h: frame loop and sequence done with a read error fig 9. pcu9669 i 2 c status codes 80h chstatus register, interrupt requested; interrupt goes low at the stop data a any number of data bytes and their associated acknowledge bits from master to slave from slave to master statusx_[n] register, no interrupt a last byte is nack sla 0 s wa a data s sla 0 r 01h data a data a n s w p 002aaf619 b.) transactions with wemsk and remsk = 1 20h sla 0 s wa a data sla 0 r data a data a data available to be read on parallel bus s sla 1 w datan sla n p a.) transactions with wemsk and remsk = 0 00h 01h 08h 20h a a p 04h 10h a a p 10h s 20h a a p f8h 20h a a p 04h s w datan 20h a a p 08h 20h a a p 04h p 80h 00h 20h 08h 20h a a 04h s 02h 10h a a 10h data available to be read on parallel bus 02h sla 1 20h a a 08h datan a s sla n s 02h 02h w 20h a a 08h datan a e0h c0h a0h c0h 01h 01h
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 38 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller status and configuration registers are not shown. shaded areas are comments/indexes that are not user-accessible. fig 10. pcu9669 sequence block diagram; sample sequence loaded 002aaf620 00h tranconfig - 01h 02h : 03h 3dh 3eh 3fh 01h 40h 05h 10h : 08h 10h 05h 08h transaction count transaction 0 length, 1 byte transaction 1 length, 5 bytes transaction 2 length, 16 bytes transaction 3 length, 8 bytes : transaction 61 length, 16 bytes transaction 62 length, 5 bytes transaction 63 length, 8 bytes 00h slatable 01h 02h : 03h 3dh 3eh 3fh 10h 11h 40h : e0h 20h 33h 20h slaw slar slaw slaw : slaw slar slaw the slave address plus transaction count, direction bit, the transaction length and the transaction data make up one complete serial bus transaction or sequence. data 00h 10h 00h 00h 00h 02h 55h transaction 0, data byte 0 transaction 1, data byte 0 transaction 1, data byte 1 transaction 1, data byte 2 transaction 1, data byte 4 transaction 2, data byte 0 transaction 2, data byte 1 : aah : transaction 2, data byte 15 :: 44h transaction 63, data byte 0 aah transaction 63, data byte 1 :: 55h transaction 63, data byte 7 :: :: :: :: unused memory space internal memory pointer a00h or f00h sequence read and write data memory space internal memory pointer 0000h the memory pointers are managed internally by the buffer controller. number of slave addresses to be included in a sequence 00h transaction 1, data byte 3 transaction length corresponding to each slave address in the slatable slave address plus direction bit
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 39 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 8.2 read transactions (fm+ channel only) many i 2 c-bus slave devices need a command or regist er offset to setup a read operation. in this case, a read transaction is actually a multi-part transaction consisting of a write transaction followed by a read transaction. this is done by setting the transactions in that order when programming the sequence. if no write is required prior to a read, then the read transaction can be placed in any location of the sequence. once the read tran saction is completed (i .e., the tr bit is cleared to 0) the data is immediately available for the host to retrieve it on the parallel bus. 8.3 stopping a sequence if the host needs to stop the execution of a sequence, it should set the sto bit in the control register. fo r write transactions, the host will issue a stop after the acknowledge cycle of the current byte being transferred on the serial bus. for read transactions, if the host sets the sto bit wh ile an address + read bit (sla+r) is sent, the controller will complete the read of one byte by sending 9 clocks and a nack on the ninth clock before sending the stop condition. if the host se ts the sto bit while a read transaction is in progress, the current byte will be nacked before sending a stop condition. no interrupts will be generated and all t he status registers will be up to date. the sequence done bit (sd) will be set to indicate to the host that the stop condition was completed and the bus is idle. the se quence done a nd the frame loop done will be set if the channel is in loop mode (framecnt ? 1) and a sto or stoseq bit is set. if the host issues a stop (by setting the sto) in the middle of a sequence followed by a start (by setting the sta), then the cont roller will re-send the sequence from the beginning, not from the point where the sequence was last stopped. 8.4 looping a sequence a sequence can be set to automatically loop several times using the framecnt and one of the following: ? the refrate register. the refrate register contains the value of the refresh rate which is timing required between the star t of two sequences. the refresh rate is derived from the internal clock of the bus controller. if the refrate is programmed to 00h, the sequences will be looped back-to-back. ? trigger enable (te) bit. when te is set, the refresh rate is controlled by the external trigger input and the contents of the refr ate registers is ignored. there is no maximum timing requirement for the trigger interval. the framecnt register sets the number of times th e sequence will be repeated. a frame is defined as a sequence associated wit h its respective refresh rate. as described above, the frame refresh rate is determined by the refrate register or an external trigger source. during looping, there is no host intervention required and all status and error reporting remains active. the sd (sequence done) bit ca n be masked to avoid getting interrupted each time a frame is completed while the other error reporting bits remain unmasked. in this manner, normal transactions can run wit hout host intervention and errors will be reported at the stop of the current byte where the error occurred.
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 40 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller once the framecnt values is reached, the fld bit in the chstatus register is set and no further transactions will be executed and th e channel will go to the idle state. the fld interrupt can be masked with the fldmsk bit in the ctrlintmsk register. the host can poll the ctrlstatus register to check if the channel is active (looping) or if it is idle. for indefinite or long term looping the host can do the following: 1. a sequence can be set to loop indefinitely by setting the framecnt register to 00h. each frame will be sent out following the refrate settings or the trigger input if the te bit is set. to end the loop mode, the host sets the sto or stoseq bits in the control register. 2. a frame will be sent out c ontinuously and back-to-back if framecnt and refrate are set to 00h. to end the loop mode, the hose sets the sto or stoseq bits in the control register. 8.4.1 looping with refrate control when using the refrate register (te bit is 0) the refresh rate timing is controlled internally. once the sta bit is set, the st art command will be immediately sent on the serial bus followed by the sequence. thereafter, the controller will issue a start command followed by the stored sequence every time the refrate value is reached. it is important to program enough time in the refrate to allow a complete sequence to reach the sequence done state. if the refresh rate is not long enough, the frame error (fe) bit will be set and an interrupt will be ge nerated. the fe bit is maskable, however, masking the fe bit may yield undesired results on the serial interface. if the fe bit is masked, the loop mode will continue to operate and the fe flag will remain set. to exit the loop mode, the sto or th e stoseq bit should be set. 8.4.2 looping with trigger control the pcu9669 has one trigger input. the trigger enable (te) bit in the control register is used to control the use of external triggering. once enabled , the trigger will override the contents of the refrate register, and will st art triggering when the sta bit is set. therefore, a significant time delay can occur between setting the sta bit and the detection of a trigger. when a trigger edge is detected, the controller will issue a start command and the stored sequence will be tran sferred on the serial bus. the trigger will control the timing of the frame, therefore, eno ugh time should be allowed by the trigger to allow the sequence to reach the sequence done state. if a trigger edge is detected while a sequence is actively being transmitted on the bus, the frame error (fe) bit will be set and an interr upt will be generated. the fe bit is maskable, however, masking the fe bit may yield undesired results on the serial interface. if the fe bit is masked, the loop mode will continue to operate and the fe flag will remain set. the polarity of the trigger edge detect is controlled by the tp bit in the control register. to exit the trigger mode, the sto or the stoseq bit should be set.
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 41 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 8.5 bus errors (fm+ channel only) bus errors are a rare occurrence in a well designed i 2 c-bus system. the pcu9669 has a robust error detection mechanism that detects hang-ups such as if sda or scl is pulled low by an external source, or if an illegal start or stop condition appe ars on the bus. 8.5.1 i 2 c-bus obstructed by a low level on sda (dae) an i 2 c-bus hang-up occurs if sda is pulled low by an uncontrolled source (e.g., a slave device out of bit synchronization). if the sd a line is obstructed by another device on the bus, the problem can be solved by transmitting additional clock pulses on the scl line (see figure 11 ). the sda stuck fault detection is only active during a start or repeated-start condition. when the error is detected, if the auto-recovery bit is set (ar = 1), the pcu9669 sends out nine clock pulses followed by the stop condition (see figure 11 ). if the sda line is released by the slave pulling it low, a normal start condition is transmitted by the pcu9669, the ta bit is set in the statusx_[n] register and the serial transfer continues. if the sda line is not released by the slave pulli ng it low, then the pcu9669 concludes that there is a bus error, sets the dae bit in th e chstatus register, generates an interrupt signal, and releases the scl and sda lines. if the auto-recovery bit is reset (ar = 0) during error detection, the pcu9669 loads the bus error (sets the dae bit in the chstatus register), generates an interrupt signal, and releases the scl and sda lines. after the host re ads the status register, it can force a bus recovery sequence by setti ng the bus recovery bit to 1 (br = 1). the pcu9669 will transmit additional clock pulses on the scl line and the host must re-start the transmission by setting the sta bit. if a repeated start condition is transmitted while sda is obstructed (pulled low), the pcu9669 performs the same action as described above. in each case, the ta bit is set after a successful start condition is transmi tted and normal serial transfer continues. note that the host is not involved in so lving these bus hang-up problems when the auto-recovery bit is set (ar = 1). when a host is unable to recover the bus by having the ar bit set or forcing a bus recovery sequence by setting the bus recovery by setti ng the br, then it may be necessary to reset the slaves or the system. remark: if the ar bit is set and an sda stuc k low is detected, the transaction will continue normally after an auto-recovery from the failed location in the sequence. if the ar bit is zero and a manual bus recovery is performed, the transaction will be re-started from the beginning of the sequence.
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 42 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 8.5.2 i 2 c-bus obstructed by a low level on scl (cle) an i 2 c-bus hang-up occurs if sda or scl is pu lled low by an uncontrolled source. if the scl line is obstructed (pulled low) by a device on the bus, no further serial transfer is possible, and the pcu9669 cannot resolve this type of problem. when this occurs, the problem must be resolved by the device that is pulling the scl bus line low. to resolve this type of a problem, resetting the slaves or the system may be required. when the scl line stays low for a period equal to the time-out value, the pcu9669 concludes that this is a bus error and behaves in a manner described in section 7.5.1.15 ? timeout ? time-out register ? . the bus recovery function (set ting the br bit) will not have any effect on an scl stuck low error. 8.5.3 illegal start or stop (sse) the illegal start or stop detection is active immediately after the ctrlrdy register is set to 00h at device start-up. the sse cond ition will be monitored and detected at any time the bus controller is not the one initiating the transition. an sse occurs when a start or stop condit ion is present at an illegal position. examples of illegal positions are during the serial transfer of an address byte, a data or an acknowledge bit. when an sse condition is detected, the pcu9 669 releases the sda and scl lines, sets the interrupt flag, an d sets the sse bit in the channel status register (chstatus). 8.6 power-on reset when power is applied to v dd , an internal power- on reset holds the pcu9669 in a reset condition until v dd has reached v por . at this point, the reset condition is released and the pcu9669 goes to the power-up initializatio n phase where the following operations are performed: 1. the oscillator and pll will be re-initialized. 2. internal register init ialization is performed. 3. the memory space will be zeroed out. fig 11. recovering from a bus obstruction caused by a low level on sda (ar = 1) 123456789 002aaf621 stop condition start condition sda line scl line s fault detected at start line held low by slave line released by slave, bus recovered line driven by master p 9 clocks driven by master
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 43 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller the complete power-up initialization phase takes t rst to be performed. during this time, writes to the pcu9669 through the parallel po rt are ignored. howe ver, the parallel port can be read. this allows the device connected to the parallel port of the pcu9669 to poll the ctrlrdy register. 8.7 global reset reset of the pcu9669 to its default state can be performed in 2 different ways: ? by holding the reset pin low for a minimum of t w(rst) . ? by using the parallel software reset sequence as described in figure 12 . the host must write to the ctrlpreset register of the target channel in two successive parallel bus writes to the bus controller. the first byte is a5h and the second byte is 5ah. the reset hardware pin and the global software reset function behave the same as the power-on reset. a comp lete power-up initia lization phase will be perf ormed as defined in section 8.6 . the reset pin has an internal pull-up resistor (through a series diode) to guarantee proper operation of the device. this pin should not be left floating and should always be driven. fig 12. parallel software reset sequence 002aaf622 a[7:0] ctrlpreset register selected d[7:0] a5h data byte 1 5ah data byte 2 wr if d[7:0] a5h, following byte is ignored and reset is aborted. if d[7:0] 5ah, reset is aborted. if data 1 = a5h and data 2 = 5ah, pcu9669 is reset to its default state. internal global reset signal ce
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 44 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 8.8 channel reset in addition to the above chip reset options, each channel can be individually reset by programming the preset register for that ch annel as described in figure 13 . the channel will reset to its default power-up state. the host must write to the preset register of the target channel in two successi ve parallel bus writes to the bus controller. the first byte is a5h and the second byte is 5ah. fig 13. i 2 c-bus channel parallel software reset sequence 002aaf623 d[7:0] a5h data byte 1 5ah data byte 2 wr a[7:0] channel preset register selected if d[7:0] a5h, following byte is ignored and reset is aborted. if d[7:0] 5ah, reset is aborted. if data 1 = a5h and data 2 = 5ah, pcu9669 is reset to its default state. internal channel reset signal ce
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 45 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 8.9 i 2 c-bus timing diagrams the diagrams figure 14 and figure 15 illustrate typical timing diagrams for the pcu9669. pcu9669 writes data to slave. (1) 7-bit address + r/w = 0 byte and number of bytes sent = value programmed in transaction length register in tranconfig register. fig 14. bus timing diag ram; write transactions pcu9669 reads data from slave. (1) number of bytes received = value programmed in the transaction length register in tranconfig. fig 15. bus timing diagram; read transac tions (does not apply to the ufm channel) n byte (1) ack scl sda int start condition 7-bit address (1) r/w = 0 from slave receiver first byte (1) ack ack stop condition 002aaf301 interrupt (after stop) n byte (1) ack scl sda int start condition 7-bit address r/w = 1 from slave first byte (1) ack no ack stop condition 002aaf624 from pcu9669 interrupt (after stop)
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 46 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 9. characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up re sistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 9.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 16 ). 9.1.1 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is hi gh is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p) (see figure 17 ). 9.2 system configuration a device generating a message is a ?transmitter ?; a device receiving is the ?receiver?. the device that controls the message is the ?master? and the devices which are controlled by the master are the ?slaves? (see figure 18 ). fig 16. bit transfer mba607 data line stable; data valid change of data allowed sda scl fig 17. definition of start and stop conditions mba608 sda scl p stop condition s start condition
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 47 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 9.3 acknowledge the number of data bytes transferred betwe en the start and the stop conditions from transmitter to receiver is not limited. ea ch byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must gen erate an acknowledge af ter the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transm itter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse; set-up and hold times must be taken into account. a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge on the last byte that has been cloc ked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. fig 18. system configuration 002aaf625 pcu9669 master transmitter/ receiver slave receiver slave transmitter/ receiver slave receiver slave transmitter/ receiver sda scl i 2 c-bus multiplexer slave transmitter/ receiver fig 19. acknowledgement on the i 2 c-bus 002aaa987 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 48 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 10. characteristics of the i 2 c-bus ? ultra fast-mode (ufm) the pcu9669 ufm bus is a 2-wire push-pull serial bus that operates from 50 khz to 5 mhz transmitting data in one direction. the ufm protocol is based on the i 2 c-bus protocol that consists of a start, slave address, command bit, ninth clock, and a stop bit. the command bit is a ?write? only, and the data bit on the ninth clock is driven high, ignoring the ack cycle due to the unidirectional nature of the bus. the 2-wire pull-pull drivers consists of a ufm clock (uscl) and data (usda), requiring external series resistors to allow proper line termination. the ufm bus is designed to be used in high performance single master multi-drop applications. the external resistors are chosen based upon the characteristic impedance of the ufm bus. for example, if the characteristic input impedance of the line is 175 ? , a series resistance of 175 ? can be used. since the output resistance of the driver is approximately 50 ? , the value of the series resist ance used would then be 125 ? . the final value of the resistance also depends upon the electrical length of the bus and the signal settling time required to meet the ufm ti ming characteristics. larger values result in longer time for the signal to settle to its final valid value. lower values can result in overshoot and ringing on the bus. careful consideration must be made in designing the i 2 c-bus routing and selecting the series resistance. 10.1 bit transfer one data bit is transferred during each cl ock pulse. the data on the usda line must remain stable during the high period of the cl ock pulse as changes in the data line at this time will be interpreted as control signals (see figure 21 ). fig 20. simplified schematic of uscl, usda outputs 002aaf143 r s , external uscl or usda pin v ss v dd(io) fig 21. ufm i 2 c-bus bit transfer 002aaf626 data line stable change of data allowed usda uscl sdadly sclper
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 49 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 10.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p) (see figure 22 ). 10.3 acknowledge (ninth clock) the ufm bus functions as a transmitter only (unidirectional). the number of data bytes transferred between the start and the stop co nditions from transmitter to receiver is not limited. each byte of eight bits of real da ta is followed by a dummy bit which is a high level put on the bus by the transmitter, whic h also generates an associated clock pulse. since the ufm bus is unidirectional, a slave receiver shall not generate an acknowledge pulse. the slave uscln and usdan pins are input only. fig 22. definition of start and stop conditions for ufm i 2 c-bus 002aaf145 usda uscl p stop condition s start condition fig 23. acknowledgement on the ufm i 2 c-bus 002aaf144 start condition 9 8 2 1 clock pulse for acknowledgement data output by transmitter scl from master master drives the line high on 9th clock cycle. slave never drives the usda line.
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 50 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 11. jtag port the pcu9669 has a jtag ieee 1149.1 compliant port. all signals (tdi, tms, tck, trst and tdo) are accessible. only extest functions are enabled, for example to conduct board-level continuity tests. device deb ug/emulation functionality such as intest commands are not supported. the jtag port is used for boundary scan testing (i.e., opens/shorts) during pcb manufacturing. the following extest jtag instructions are supported: ? bypass ? extest ? idcode ? sample ? preload ? clamp ? highz if the jtag boundary scan is not being used, then the jtag pins must be held in the following states: ? tdi, tck, tms: v dd ? trst : v ss
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 51 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 12. application design-in information 12.1 specific applications the pcu9669 is a parallel bus to i 2 c-bus controller that is designed to allow ?smart? devices to interface with i 2 c-bus or smbus components, where the ?smart? device does not have an integrated i 2 c-bus port and the designer does not want to ?bit-bang? the i 2 c-bus port. the pcu9669 can also be used to add more i 2 c-bus ports to ?smart? devices, provide a higher frequency, lowe r voltage migration path for the pcf8584, pca9564 and pca9665 and convert 8 bits of parallel data to a serial bus to avoid running multiple traces across the printed-circuit board. fig 24. application diagram using the 80c51 002aaf481 pcu9669 80c51 decoder d0 to d7 ale ce rd wr int a0 scl0 sda0 a1 reset slave int reset address bus v dd v dd 8 v ss v dd(io) v dd v dd v ss slave uscl1 usda1 slave uscl2 usda2 slave v dd(io) a2 a3 a4 a5 a6 a7 trig
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 52 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 12.2 add i 2 c-bus port as shown in figure 25 , the pcu9669 converts 8-bits of parallel data into a single master capable i 2 c-bus port for microcontrollers, microp rocessors, custom asics, dsps, etc., that need to interface with i 2 c-bus or smbus components. 12.3 add additional i 2 c-bus ports the pcu9669 can be used to convert 8-bit parallel data into additional single master capable i 2 c-bus port as shown in figure 26 . it is used if the microcontroller, microprocessor, custom asic, ds p, etc., already have an i 2 c-bus port but need one or more additional i 2 c-bus ports to interface with more i 2 c-bus or smbus components or components that cannot be located on the same bus (e.g., 100 khz and 400 khz slaves on different buses so that each bus can operate at its maximum potential). fig 25. adding i 2 c-bus port application microcontroller, microprocessor, or asic control signals 8 bits data pcu9669 sda0 scl0 002aaf482 usda1 uscl1 usda2 uscl2 fig 26. adding additional i 2 c-bus ports application control signals 8 bits data pcu9669 sda0 scl0 002aaf483 slave microcontroller, microprocessor, or asic usda1 uscl1 slave usda2 uscl2 slave master i 2 c-bus
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 53 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 13. limiting values [1] 5.5 v steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 v steady stat e voltage tolerance on inputs and outputs when no supply voltage is present. 14. static characteristics table 37. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.3 +4.6 v v dd(io) input/output supply voltage power supply reference for i 2 c-bus i/o pins ? 0.3 +7.0 v v i input voltage parallel bus interface ? 0.3 +4.6 v i 2 c-bus pins [1] ? 0.3 +7.0 v i i input current any input ? 10 +10 ma i o output current any output ? 10 +10 ma i osh high-level short-circuit output current i/o d0 to d7 - 106 ma i osl low-level short-circuit output current i/o d0 to d7 - 110 ma p tot total power dissipation - 300 mw p/out power dissipation per output - 50 mw t stg storage temperature ? 65 +150 ?c t amb ambient temperature operating ? 40 +85 ?c table 38. static characteristics v dd = 3.0 v to 3.6 v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit supply v dd supply voltage monotonic supply during power-up and power-down with a ramp time (t ramp ): 5 ? s pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 54 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller [1] 5.5 v steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 v steady stat e voltage tolerance on inputs and outputs when no supply voltage is present. inputs wr , rd , a0 to a7, ce , trig v il low-level input voltage 0 - 0.3v dd v v ih high-level input voltage [1] 0.7v dd -3.6 v v hys hysteresis voltage 0.1v dd -- v i l leakage current input; v i =0vor3.6v ? 1-+1 ? a c i input capacitance v i =v ss or v dd -2.04.5pf input reset v il low-level input voltage 0 - 0.3v dd v v ih high-level input voltage [1] 0.7v dd -3.6 v v hys hysteresis voltage 0.1v dd -- v i l leakage current input; v i =0vor3.6v ? 1-+75 ? a c i input capacitance v i =v ss or v dd -2.04.5pf inputs/outputs d0 to d7 v il low-level input voltage 0 - 0.3v dd v v ih high-level input voltage 0.7v dd -3.6 v i oh high-level output current v oh =v dd(io) ? 0.4 v 3.2 - - ma i ol low-level output current v ol =0.4v 2.0 - - ma i l leakage current input; v i = 0 v or 5.5 v ? 1-+1 ? a c io input/output capacitance v i =v ss or v dd -2.85pf usdan and uscln i ol low-level output current v ol =0.4v 5 - - ma i oh high-level output current v oh =v dd(io) ? 0.4 v 4.8 - - ma c io input/output capacitance v i =v ss or v dd(io) -5.67pf r on on resistance - 50 - ? i l leakage current v dd =3.6v ? 1-+1 ? a v dd =5.5v ? 10 - +10 ? a sdan and scln v il low-level input voltage 0 - 0.3v dd(io) v v ih high-level input voltage [1] 0.7v dd(io) -5.5 v i l leakage current input/output; v i =0vor3.6v ? 75 - +1 ? a input/output; v i =0vor5.5v ? 75 - +1 ? a i ol low-level output current v ol =0.4v 30 - - ma c io input/output capacitance v i =v ss or v dd(io) -5.67pf output int i ol low-level output current v ol =0.4v 6.0 - - ma i l leakage current v o = 0 v or 3.6 v ? 1-+75 ? a c o output capacitance v i =v ss or v dd -3.85.5pf table 38. static characteristics ?continued v dd = 3.0 v to 3.6 v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 55 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 15. dynamic characteristics [1] parameters are valid over sp ecified temperature and voltage range. [2] all voltage measurements are referenced to ground (v ss ). for testing, all inputs swing between 0 v and 3.0 v with a transition time of 5 ns maximum. all time measurements are referenced at input voltages of 1.5 v and output voltages shown in figure 27 and figure 29 . [3] test conditions for outputs: c l =50pf; r l = 500 ? , except open-drain outputs. test conditions for open-drain outputs: c l =50pf; r l =1k ? pull-up to v dd . [4] resetting the device while actively communicating on the bus may cause glitches or an errant stop condition. [5] upon reset, the full delay will be the sum of t rst and the rc time constant of the sda and scl bus. table 39. dynamic characteristics (3.3 volt) [1] [2] [3] v dd =3.3v ? 0.3 v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit initialization timing t init(po) power-on initialization time v dd ? 3.0 v - - 650 ? s t init initialization time channel initialization time from channel software reset --70 ? s controller initialization time from por, reset , or global software reset inactive --650 ? s reset timing t w(rst) reset pulse width 4 - - ? s t rst reset time [4] [5] 1.5 - - ? s int timing t as(int) interrupt assert time - - 500 ns t das(int) interrupt de-assert time - - 100 ns trig timing t w(trig) trigger pulse width high or low 100 - - ns bus timing (see figure 27 and figure 29 ) t su(a) address set-up time to rd , wr low 0 - - ns t h(a) address hold time from rd , wr low 14 - - ns t su(ce_n) ce set-up time to rd , wr low 0 - - ns t h(ce_n) ce hold time from rd , wr low 0 - - ns t w(rdl) rd low pulse width 40 - - ns t w(wrl) wr low pulse width 40 - - ns t d(dv) data valid delay time after rd and ce low - - 45 ns t d(qz) data output float delay time after rd or ce high - - 7 ns t su(q) data output set-up time before wr high 5 - - ns t h(q) data output hold time after wr high 2 - - ns t w(rdh) rd high pulse width 40 - - ns t w(wrh) wr high pulse width 40 - - ns
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 56 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller fig 27. bus timing (read cycle) fig 28. parallel bus timing (write cycle) a0 to a7 ce rd d0 to d7 (read) 002aaf458 t su(a) t h(a) t su(ce_n) t h(ce_n) t w(rdl) t w(rdh) float float not valid valid t d(dv) t d(qz) a0 to a7 ce 002aaf459 t su(a) t h(a) t su(ce_n) t h(ce_n) wr valid t w(wrh) d0 to d7 (write) t su(q) t h(q) t w(wrl)
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 57 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller v m =1.5v v x =v ol +0.2v v y =v oh ? 0.2 v v ol and v oh are typical output voltage drops that occur with the output load. fig 29. data timing 002aaf172 t d(qlz) t d(qhz) outputs floating outputs enabled outputs enabled dn output low-to-float float-to-low dn output high-to-float float-to-high rd, ce input v i v ol v oh v dd v m v m v x v y v m v ss v ss t d(qzl) t d(qzh) v m
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 58 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller [1] minimum scl clock frequency is limited by the bus time-out feature, generates a cle error if the scl is held low for the tim eout period. [2] t vd;ack = time for acknowledgement signal from scl low to sda (out) low. [3] t vd;ack is not applicable to the ultra fast-mode (ufm) i 2 c-bus. [4] t vd;dat = minimum time for sda data out to be valid following scl low. [5] a master device must internally provide a hold time of at least 300 ns for the sda signal (refer to the v il of the scl signal) in order to bridge the undefined region scl?s falling edge. does not apply to the ufm channel. [6] the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. th is allows series protection resistors to be connected between the sdan and the scln pins and the sda/scl bus lines without exceeding the maximum specified t f . does not apply to the ufm channel. [7] c b = total capacitance of one bus line in pf. [8] typical rise/fall times for uf m signals is 25 ns measured from the 20 % level to the 80 % (rise time) or from the 80 % level to the 20 % level (fall time). [9] input filters on the sdan and scln inputs suppress noise spikes less than 50 ns. [10] t sp is not applicable to the ultra fast-mode (ufm) i 2 c-bus. table 40. i 2 c-bus frequency and timing specifications all the timing limits are valid within the operating supply voltage and ambient temperature range; v dd =2.5v ? 0.2 v and 3.3 v ? 0.3 v; t amb = ? 40 ? c to +85 ? c; and refer to v il and v ih with an input voltage of v ss to v dd . symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus fast-mode plus i 2 c-bus ultra fast-mode i 2 c-bus unit min max min max min max min max f scl scl clock frequency [1] 0 100 0 400 0 1000 0 5000 khz t buf bus free time between a stop and start condition 4.7 - 1.3 - 0.5 - 0.08 - ? s t hd;sta hold time (repeated) start condition 4.0 - 0.6 - 0.26 - 0.05 - ? s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - 0.26 - 0.05 - ? s t su;sto set-up time for stop condition 4.0 - 0.6 - 0.26 - 0.05 - ? s t hd;dat data hold time 0 - 0 - 0 - 10 - ns t vd;ack data valid acknowledge time [2] 0.1 3.45 0.1 0.9 0.1 0.45 - [3] - [3] ? s t vd;dat data valid time [4] 100 - 100 - 100 - 10 - ns t su;dat data set-up time 100 - 100 - 100 - 30 - ns t low low period of the scl clock 4.7 - 1.3 - 0.5 - 0.05 - ? s t high high period of the scl clock 4.0 - 0.6 - 0.26 - 0.05 - ? s t f fall time of both sda and scl signals [5] [6] -30020+0.1c b [7] 300 - 120 - [8] 50 ns t r rise time of both sda and scl signals - 1000 20 + 0.1c b [7] 300 - 120 - [8] 50 ns t sp pulse width of spikes that must be suppressed by the input filter [9] -50 - 50 - 50- [10] - [10] ns
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 59 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller fig 30. definition of timing on the i 2 c-bus sda scl 002aab271 t f s sr p s t hd;sta t low t r t su;dat t f t hd;dat t high t su;sta t hd;sta t sp t su;sto t r t buf rise and fall times refer to v il and v ih . fig 31. i 2 c-bus timing diagram scl sda t hd;sta t su;dat t hd;dat t f t buf t su;sta t low t high t vd;ack 002aac696 protocol start condition (s) bit 7 msb bit 6 bit n bit 0 ac kno wledge (a) 1 /f scl t r t vd;dat t su;sto stop condition (p)
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 60 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 16. test information test data are given in ta b l e 4 1 . r l = load resistance. c l = load capacitance includes jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generators. fig 32. test circuitry for switching times table 41. test data test conditions load s1 c l r l t d(dv) , t d(qz) dn outputs active low 50 pf 500 ? v dd ? 2 dn outputs active high 50 pf 500 ? open test data are given in ta b l e 4 2 . r l = load resistance. c l = load capacitance includes jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generators. fig 33. test circuitry for open-drain switching times table 42. test data int pin test load s1 c l r l t as(int) 50 pf 1 k ? v dd t das(int) 50 pf 1 k ? v dd pulse generator v o c l 50 pf r l 500 002aac694 r t v i v dd dut r l 500 v dd 2 open v ss pulse generator v o c l 50 pf r l 1 k 002aac695 r t v i v dd dut v dd open v ss
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 61 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 17. package outline fig 34. package outline sot313-2 (lqfp48) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1)(1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 62 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 18. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling ensure that the appropriate precautions are taken as described in jesd625-a or equivalent standards. 19. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 19.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 19.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 19.3 wave soldering key characteristics in wave soldering are:
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 63 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 19.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 35 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 4 3 and 44 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 35 . table 43. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 44. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 64 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 20. abbreviations msl: moisture sensitivity level fig 35. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 45. abbreviations acronym description asic application specific integrated circuit cdm charged-device model cpu central processing unit dsp digital signal processor esd electrostatic discharge fm+ fast-mode plus hbm human body model i 2 c-bus inter-integrated circuit bus i/o input/output led light emitting diode pll phase-locked loop smbus system management bus ufm ultra fast-mode
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 65 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 21. revision history table 46. revision history document id release date data sheet status change notice supersedes pcu9669 v.2 20110701 product data sheet - pcu9669 v.1 modifications: ? table 40 ? i 2 c-bus frequency and timing specifications ? , table note [8] : unit of measure is corrected from ?25 ms? to ?25 ns?. pcu9669 v.1 20110606 product data sheet - -
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 66 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 22. legal information 22.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 22.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 22.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 67 of 69 nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 22.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 23. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
pcu9669 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 2 ? 1 july 2011 68 of 69 continued >> nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller 24. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 internal oscillator and pll . . . . . . . . . . . . . . . . 6 7.3 buffer description . . . . . . . . . . . . . . . . . . . . . . . 6 7.3.1 buffer management assumptions . . . . . . . . . . . 7 7.3.2 buffer sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.4 error reporting and handling . . . . . . . . . . . . . . . 8 7.5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.5.1 channel registers . . . . . . . . . . . . . . . . . . . . . . 13 7.5.1.1 status0_[n], status1_[n], status2_[n] ? transaction status registers 13 7.5.1.2 control ? control register . . . . . . . . . . . . 14 7.5.1.3 chstatus ? channel status register . . . . . 17 7.5.1.4 intmsk ? interrupt mask register. . . . . . . . . 19 7.5.1.5 slatable ? slave address table register . . 20 7.5.1.6 tranconfig ? tr ansaction configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.5.1.7 data ? i 2 c-bus data register . . . . . . . . . . . . 21 7.5.1.8 transel ? transaction data buffer select register . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.5.1.9 tranofs ? transaction data buffer byte select register . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.5.1.10 bytecount ? transmitted and received byte count register . . . . . . . . . . . . . . . . . . . . . 23 7.5.1.11 framecnt ? frame c ount register . . . . . . . 23 7.5.1.12 refrate ? refresh rate register. . . . . . . . . 24 7.5.1.13 scll, sclh and sclper, sdadly ? clock rate registers. . . . . . . . . . . . . . . . . . . . . 24 7.5.1.14 mode ? i 2 c-bus mode register . . . . . . . . . . 28 7.5.1.15 timeout ? time-out register. . . . . . . . . . . . 29 7.5.1.16 preset ? i 2 c-bus channel parallel software reset register. . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.5.2 global registers . . . . . . . . . . . . . . . . . . . . . . . 30 7.5.2.1 ctrlstatus ? controller status register . . 30 7.5.2.2 ctrlintmsk ? control interrupt mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.5.2.3 device_id ? device id . . . . . . . . . . . . . . . . 32 7.5.2.4 ctrlpreset ? para llel software reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.5.2.5 ctrlrdy ? controller ready register . . . . . 33 8 pcu9669 operation . . . . . . . . . . . . . . . . . . . . . 34 8.1 sequence execution . . . . . . . . . . . . . . . . . . . 35 8.2 read transactions (fm+ channel only) . . . . . 39 8.3 stopping a sequence . . . . . . . . . . . . . . . . . . . 39 8.4 looping a sequence. . . . . . . . . . . . . . . . . . . . 39 8.4.1 looping with refrate control . . . . . . . . . . . 40 8.4.2 looping with trigger control. . . . . . . . . . . . . . 40 8.5 bus errors (fm+ channel only). . . . . . . . . . . . 41 8.5.1 i 2 c-bus obstructed by a low level on sda (dae). . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.5.2 i 2 c-bus obstructed by a low level on scl (cle) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.5.3 illegal start or stop (sse) . . . . . . . . . . . . 42 8.6 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . 42 8.7 global reset . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.8 channel reset. . . . . . . . . . . . . . . . . . . . . . . . . 44 8.9 i 2 c-bus timing diagrams. . . . . . . . . . . . . . . . . 45 9 characteristics of the i 2 c-bus . . . . . . . . . . . . 46 9.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.1.1 start and stop conditions. . . . . . . . . . . . . 46 9.2 system configuration . . . . . . . . . . . . . . . . . . . 46 9.3 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 47 10 characteristics of the i 2 c-bus ? ultra fast-mode (ufm). . . . . . . . . . . . . . . . . . . . . . . 48 10.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.2 start and stop conditions. . . . . . . . . . . . . 49 10.3 acknowledge (ninth clock) . . . . . . . . . . . . . . . 49 11 jtag port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12 application design-in information. . . . . . . . . 51 12.1 specific applications. . . . . . . . . . . . . . . . . . . . 51 12.2 add i 2 c-bus port . . . . . . . . . . . . . . . . . . . . . . 52 12.3 add additional i 2 c-bus ports . . . . . . . . . . . . . 52 13 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 53 14 static characteristics . . . . . . . . . . . . . . . . . . . 53 15 dynamic characteristics. . . . . . . . . . . . . . . . . 55 16 test information . . . . . . . . . . . . . . . . . . . . . . . 60 17 package outline. . . . . . . . . . . . . . . . . . . . . . . . 61 18 handling information . . . . . . . . . . . . . . . . . . . 62 19 soldering of smd packages . . . . . . . . . . . . . . 62 19.1 introduction to soldering. . . . . . . . . . . . . . . . . 62 19.2 wave and reflow soldering. . . . . . . . . . . . . . . 62 19.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 62 19.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 63 20 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 64
nxp semiconductors pcu9669 parallel bus to 1 channel fm+ and 2 channel ufm i 2 c-bus controller ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 1 july 2011 document identifier: pcu9669 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 21 revision history . . . . . . . . . . . . . . . . . . . . . . . . 65 22 legal information. . . . . . . . . . . . . . . . . . . . . . . 66 22.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 66 22.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 22.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 22.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 67 23 contact information. . . . . . . . . . . . . . . . . . . . . 67 24 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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